The invention is directed to an improved approach for designing, testing, and manufacturing integrated circuits.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
In recent years, constant innovation in silicon process technology has drastically reduced the price and increased the performance and functionality of integrated circuit devices, thus stimulating the development of the electronics manufacturing and information processing industries. In turn, these fast growing industries impose increasing demands on the integrated circuit design system developers for still faster, cheaper, and more powerful devices. To address these demands, many designers of electronic systems have moved to a methodology known as Block Based Design (“BBD”), in which a system is designed by integrating a plurality of existing component design blocks. These pre-designed blocks may be obtained from internal design teams or licensed from other design companies. Moreover, pre-designed blocks may be developed to meet different design requirements and constraints.
Many companies and organizations have created entire libraries of component design blocks and other units of electronic design (also referred to in the art as “intellectual property blocks”, “IP blocks”, “IP components”, or “cores”), and have created businesses out of licensing or selling these IP blocks to other companies that use these design blocks to create an electronic product. As of the filing of this application, there exist a large number of companies that supply such IP blocks to customers, and many thousands of such IP blocks available to be integrated into a customer's own design.
One of the significant challenges faced by a modern designer is that, given the large number of potential suppliers of IP blocks, how the designer can best and most efficiently identify which of the suppliers is able to provide an IP block that will suit the needs of the designer for a given design project. This is not a trivial problem given the existence of such a large number of vendors and suppliers of IP blocks and the even larger number of IP blocks that are available for licensing or purchase. The fact that certain hard macros are available on specific, predefined processes adds another layer of complexity in terms of IP selection.
There are existing web sites and systems that provide portals for connecting suppliers and consumers of IP blocks together. These portals (“IP portals”) provide a facility where, even if the user cannot identify or locate the suitable IP or IP vendor on his or her own, the portal provides a framework for establishing communications between the consumer and any appropriate IP vendors for the requested IP. An example of such an approach for connecting IP consumers with IP providers is described in co-pending U.S. application Ser. No. 12/252,577, now U.S. Pat. No. 8,156,453, filed on Oct. 16, 2008, entitled “METHOD AND SYSTEM IDENTIFYING AND LOCATING IP BLOCKS AND BLOCK SUPPLIERS FOR AN ELECTRONIC DESIGN”, which is here incorporated by reference in its entirety.
Conventionally, once the IP consumer has identified a set of IP blocks that are potentially usable in his/her electronic design, the IP consumer must then engage in a highly manual and potentially cumbersome process involving multiple complicated stages in an attempt to see if the identified IP blocks would in fact be suitable for the electronic design. For example, the IP consumer may need to individually deal with each IP vendor to obtain detailed information about each and every one of the potentially usable IP blocks (with the required information potentially ranging from technical to legal to business terms). The user would also need to make sure that an adequate set of design tools and system resources are then available utilize those IP blocks. Only then can the user even begin to start the process of incorporating the IP blocks into the electronic design for the detailed feasibility analysis. After engaging in this lengthy process, the user may end up discovering that the selected IP blocks are actually not adequate for the intended design. The entire process is highly non-standard, and indeed, the differing situations for each individual IP consumer makes the job even more complicated to configure and set up for those IP consumers.
As is evident, this situation can conventionally create a highly inefficient process that negatively affects the IP consumer's ability to effectively identify the exact set of IP that can or should be used in his/her design. In addition, this situation also negatively affects the ability of the IP vendors to market the IP blocks to IP consumers that really should be the customers for their IP block products.